[求助]关于xilinx生成代码的问题

[kakacj]

我前几天安装的ISE，试图应用simulink搭建的框图产生verilog代码，但是在产生代码的过程中总会报错，（后来我用别人可以生成代码的的框图运行，还是同样错误），我觉得这不是框图问题，但是软件安装过程中没有什么问题，大家有谁遇到过这种问题没，期待指教，交流。
错误大概是这样的，说产生代码过程（在网表产生时出错）出现异常，特别指出是XNetlistEngine。com.xilinx.sysgen.netlist.f:不能运行（Couldn't run）。

上面的是我翻译过来的报错信息，具体如下：


Begin generation
Checking model status
Checking simulation times
Performing compilation and generation

*** ERROR ***
Errors occurred during netlist generation.
Error using ==> sim
Error reported by S-function 'sysgen' in 'add_text/Gateway In':
Summary of errors from all sources:
(NOTE: None of the errors were associated with a particular block;
the block reporting this summary was chosen at random.)
--------------------------------------------------------------------------
Summary of Errors:
Error 0001: caught standard exception
Block: Unspecified
--------------------------------------------------------------------------
Error 0001:
Reported by:
Unspecified
Details:
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.f: couldn't run
c:\Xilinx/bin/nt/coregen -b makeproj at
D:/MATLAB/R2006a/toolbox/xilinx/sysgen/scripts/SgGenerateCores.pm
line 721.
--------------------------------------------------------------------------.



大家帮我分析下是哪里出的错，应该怎么解决才好，如果恰好遇到过这种问题，希望能说下具体的解决方案，谢谢。
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